src/constants-arm.h
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00001 // Copyright 2008 the V8 project authors. All rights reserved. 00002 // Redistribution and use in source and binary forms, with or without 00003 // modification, are permitted provided that the following conditions are 00004 // met: 00005 // 00006 // * Redistributions of source code must retain the above copyright 00007 // notice, this list of conditions and the following disclaimer. 00008 // * Redistributions in binary form must reproduce the above 00009 // copyright notice, this list of conditions and the following 00010 // disclaimer in the documentation and/or other materials provided 00011 // with the distribution. 00012 // * Neither the name of Google Inc. nor the names of its 00013 // contributors may be used to endorse or promote products derived 00014 // from this software without specific prior written permission. 00015 // 00016 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00017 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00018 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 00019 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 00020 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 00021 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00022 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 00023 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 00024 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00025 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00026 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00027 00028 #ifndef V8_CONSTANTS_ARM_H_ 00029 #define V8_CONSTANTS_ARM_H_ 00030 00031 namespace assembler { namespace arm { 00032 00033 // Defines constants and accessor classes to assemble, disassemble and 00034 // simulate ARM instructions. 00035 // 00036 // Constants for specific fields are defined in their respective named enums. 00037 // General constants are in an anonymous enum in class Instr. 00038 00039 typedef unsigned char byte; 00040 00041 enum Condition { 00042 no_condition = -1, 00043 EQ = 0, 00044 NE = 1, 00045 CS = 2, 00046 CC = 3, 00047 MI = 4, 00048 PL = 5, 00049 VS = 6, 00050 VC = 7, 00051 HI = 8, 00052 LS = 9, 00053 GE = 10, 00054 LT = 11, 00055 GT = 12, 00056 LE = 13, 00057 AL = 14, 00058 special_condition = 15 00059 }; 00060 00061 00062 enum Opcode { 00063 no_operand = -1, 00064 AND = 0, 00065 EOR = 1, 00066 SUB = 2, 00067 RSB = 3, 00068 ADD = 4, 00069 ADC = 5, 00070 SBC = 6, 00071 RSC = 7, 00072 TST = 8, 00073 TEQ = 9, 00074 CMP = 10, 00075 CMN = 11, 00076 ORR = 12, 00077 MOV = 13, 00078 BIC = 14, 00079 MVN = 15 00080 }; 00081 00082 00083 enum Shift { 00084 no_shift = -1, 00085 LSL = 0, 00086 LSR = 1, 00087 ASR = 2, 00088 ROR = 3 00089 }; 00090 00091 00092 enum SoftwareInterruptCodes { 00093 // transition to C code 00094 call_rt_r5 = 0x10, 00095 call_rt_r2 = 0x11, 00096 // break point 00097 break_point = 0x20 00098 }; 00099 00100 00101 typedef int32_t instr_t; 00102 00103 00104 // The class Instr enables access to individual fields defined in the ARM 00105 // architecture. 00106 class Instr { 00107 public: 00108 enum { 00109 kInstrSize = 4, 00110 kPCReadOffset = 8 00111 }; 00112 00113 // Get the raw instruction bits 00114 inline instr_t InstructionBits() const { 00115 return *reinterpret_cast<const instr_t*>(this); 00116 } 00117 00118 inline void SetInstructionBits(instr_t value) { 00119 *reinterpret_cast<instr_t*>(this) = value; 00120 } 00121 00122 inline int Bit(int nr) const { 00123 return (InstructionBits() >> nr) & 1; 00124 } 00125 00126 inline int Bits(int hi, int lo) const { 00127 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 00128 } 00129 00130 00131 // Accessors for the different named fields used in the ARM encoding. 00132 // Generally applicable fields 00133 inline Condition ConditionField() const { 00134 return static_cast<Condition>(Bits(31, 28)); 00135 } 00136 inline int TypeField() const { return Bits(27, 25); } 00137 00138 inline int RnField() const { return Bits(19, 16); } 00139 inline int RdField() const { return Bits(15, 12); } 00140 00141 // Fields used in Data processing instructions 00142 inline Opcode OpcodeField() const { 00143 return static_cast<Opcode>(Bits(24, 21)); 00144 } 00145 inline int SField() const { return Bit(20); } 00146 // with register 00147 inline int RmField() const { return Bits(3, 0); } 00148 inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); } 00149 inline int RegShiftField() const { return Bit(4); } 00150 inline int RsField() const { return Bits(11, 8); } 00151 inline int ShiftAmountField() const { return Bits(11, 7); } 00152 // with immediate 00153 inline int RotateField() const { return Bits(11, 8); } 00154 inline int Immed8Field() const { return Bits(7, 0); } 00155 00156 // Fields used in Load/Store instructions 00157 inline int PUField() const { return Bits(24, 23); } 00158 inline int BField() const { return Bit(22); } 00159 inline int WField() const { return Bit(21); } 00160 inline int LField() const { return Bit(20); } 00161 // with register uses same fields as Data processing instructions above 00162 // with immediate 00163 inline int Offset12Field() const { return Bits(11, 0); } 00164 // multiple 00165 inline int RlistField() const { return Bits(15, 0); } 00166 // extra loads and stores 00167 inline int SignField() const { return Bit(6); } 00168 inline int HField() const { return Bit(5); } 00169 inline int ImmedHField() const { return Bits(11, 8); } 00170 inline int ImmedLField() const { return Bits(3, 0); } 00171 00172 // Fields used in Branch instructions 00173 inline int LinkField() const { return Bit(24); } 00174 inline int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); } 00175 00176 // Fields used in Software interrupt instructions 00177 inline SoftwareInterruptCodes SwiField() const { 00178 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); 00179 } 00180 00181 // Test for special encodings of type 0 instructions (extra loads and stores, 00182 // as well as multiplications). 00183 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } 00184 00185 // Special accessors that test for existence of a value. 00186 inline bool HasS() const { return SField() == 1; } 00187 inline bool HasB() const { return BField() == 1; } 00188 inline bool HasW() const { return WField() == 1; } 00189 inline bool HasL() const { return LField() == 1; } 00190 inline bool HasSign() const { return SignField() == 1; } 00191 inline bool HasH() const { return HField() == 1; } 00192 inline bool HasLink() const { return LinkField() == 1; } 00193 00194 // Instructions are read of out a code stream. The only way to get a 00195 // reference to an instruction is to convert a pointer. There is no way 00196 // to allocate or create instances of class Instr. 00197 // Use the At(pc) function to create references to Instr. 00198 static Instr* At(byte* pc) { return reinterpret_cast<Instr*>(pc); } 00199 00200 private: 00201 // We need to prevent the creation of instances of class Instr. 00202 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 00203 }; 00204 00205 00206 } } // namespace assembler::arm 00207 00208 #endif // V8_CONSTANTS_ARM_H_
