00001 // Copyright 2008 the V8 project authors. All rights reserved. 00002 // Redistribution and use in source and binary forms, with or without 00003 // modification, are permitted provided that the following conditions are 00004 // met: 00005 // 00006 // * Redistributions of source code must retain the above copyright 00007 // notice, this list of conditions and the following disclaimer. 00008 // * Redistributions in binary form must reproduce the above 00009 // copyright notice, this list of conditions and the following 00010 // disclaimer in the documentation and/or other materials provided 00011 // with the distribution. 00012 // * Neither the name of Google Inc. nor the names of its 00013 // contributors may be used to endorse or promote products derived 00014 // from this software without specific prior written permission. 00015 // 00016 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00017 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00018 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 00019 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 00020 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 00021 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00022 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 00023 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 00024 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00025 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00026 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00027 00028 00029 // Declares a Simulator for ARM instructions if we are not generating a native 00030 // ARM binary. This Simulator allows us to run and debug ARM code generation on 00031 // regular desktop machines. 00032 // V8 calls into generated code by "calling" the CALL_GENERATED_CODE macro, 00033 // which will start execution in the Simulator or forwards to the real entry 00034 // on a ARM HW platform. 00035 00036 #ifndef V8_SIMULATOR_ARM_H_ 00037 #define V8_SIMULATOR_ARM_H_ 00038 00039 #if defined(__arm__) 00040 00041 // When running without a simulator we call the entry directly. 00042 #define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) \ 00043 entry(p0, p1, p2, p3, p4) 00044 00045 // Calculated the stack limit beyond which we will throw stack overflow errors. 00046 // This macro must be called from a C++ method. It relies on being able to take 00047 // the address of "this" to get a value on the current execution stack and then 00048 // calculates the stack limit based on that value. 00049 #define GENERATED_CODE_STACK_LIMIT(limit) \ 00050 (reinterpret_cast<uintptr_t>(this) - limit) 00051 00052 #else // defined(__arm__) 00053 00054 // When running with the simulator transition into simulated execution at this 00055 // point. 00056 #define CALL_GENERATED_CODE(entry, p0, p1, p2, p3, p4) \ 00057 assembler::arm::Simulator::current()->call((int32_t)entry, (int32_t)p0, \ 00058 (int32_t)p1, (int32_t)p2, (int32_t)p3, (int32_t)p4) 00059 00060 // The simulator has its own stack. Thus it has a different stack limit from 00061 // the C-based native code. 00062 #define GENERATED_CODE_STACK_LIMIT(limit) \ 00063 (assembler::arm::Simulator::current()->StackLimit()) 00064 00065 00066 #include "constants-arm.h" 00067 00068 00069 namespace assembler { namespace arm { 00070 00071 class Simulator { 00072 public: 00073 friend class Debugger; 00074 00075 enum Register { 00076 no_reg = -1, 00077 r0 = 0, r1, r2, r3, r4, r5, r6, r7, 00078 r8, r9, r10, r11, r12, r13, r14, r15, 00079 num_registers, 00080 sp = 13, 00081 lr = 14, 00082 pc = 15 00083 }; 00084 00085 Simulator(); 00086 ~Simulator(); 00087 00088 // The currently executing Simulator instance. Potentially there can be one 00089 // for each native thread. 00090 static Simulator* current(); 00091 00092 // Accessors for register state. Reading the pc value adheres to the ARM 00093 // architecture specification and is off by a 8 from the currently executing 00094 // instruction. 00095 void set_register(int reg, int32_t value); 00096 int32_t get_register(int reg) const; 00097 00098 // Special case of set_register and get_register to access the raw PC value. 00099 void set_pc(int32_t value); 00100 int32_t get_pc() const; 00101 00102 // Accessor to the internal simulator stack area. 00103 uintptr_t StackLimit() const; 00104 00105 // Executes ARM instructions until the PC reaches end_sim_pc. 00106 void execute(); 00107 00108 // V8 generally calls into generated code with 5 parameters. This is a 00109 // convenience funtion, which sets up the simulator state and grabs the 00110 // result on return. 00111 v8::internal::Object* call(int32_t entry, int32_t p0, int32_t p1, 00112 int32_t p2, int32_t p3, int32_t p4); 00113 00114 private: 00115 enum special_values { 00116 // Known bad pc value to ensure that the simulator does not execute 00117 // without being properly setup. 00118 bad_lr = -1, 00119 // A pc value used to signal the simulator to stop execution. Generally 00120 // the lr is set to this value on transition from native C code to 00121 // simulated execution, so that the simulator can "return" to the native 00122 // C code. 00123 end_sim_pc = -2 00124 }; 00125 00126 // Unsupported instructions use Format to print an error and stop execution. 00127 void Format(Instr* instr, const char* format); 00128 00129 // Checks if the current instruction should be executed based on its 00130 // condition bits. 00131 bool ConditionallyExecute(Instr* instr); 00132 00133 // Helper functions to set the conditional flags in the architecture state. 00134 void SetNZFlags(int32_t val); 00135 void SetCFlag(bool val); 00136 void SetVFlag(bool val); 00137 bool CarryFrom(int32_t left, int32_t right); 00138 bool BorrowFrom(int32_t left, int32_t right); 00139 bool OverflowFrom(int32_t alu_out, 00140 int32_t left, 00141 int32_t right, 00142 bool addition); 00143 00144 // Helper functions to decode common "addressing" modes 00145 int32_t GetShiftRm(Instr* instr, bool* carry_out); 00146 int32_t GetImm(Instr* instr, bool* carry_out); 00147 void HandleRList(Instr* instr, bool load); 00148 void SoftwareInterrupt(Instr* instr); 00149 00150 // Read and write memory. 00151 inline uint8_t ReadBU(int32_t addr); 00152 inline int8_t ReadB(int32_t addr); 00153 inline void WriteB(int32_t addr, uint8_t value); 00154 inline void WriteB(int32_t addr, int8_t value); 00155 00156 inline uint16_t ReadHU(int32_t addr, Instr* instr); 00157 inline int16_t ReadH(int32_t addr, Instr* instr); 00158 // Note: Overloaded on the sign of the value. 00159 inline void WriteH(int32_t addr, uint16_t value, Instr* instr); 00160 inline void WriteH(int32_t addr, int16_t value, Instr* instr); 00161 00162 inline int ReadW(int32_t addr, Instr* instr); 00163 inline void WriteW(int32_t addr, int value, Instr* instr); 00164 00165 // Executing is handled based on the instruction type. 00166 void DecodeType01(Instr* instr); // both type 0 and type 1 rolled into one 00167 void DecodeType2(Instr* instr); 00168 void DecodeType3(Instr* instr); 00169 void DecodeType4(Instr* instr); 00170 void DecodeType5(Instr* instr); 00171 void DecodeType6(Instr* instr); 00172 void DecodeType7(Instr* instr); 00173 00174 // Executes one instruction. 00175 void InstructionDecode(Instr* instr); 00176 00177 // architecture state 00178 int32_t registers_[16]; 00179 bool n_flag_; 00180 bool z_flag_; 00181 bool c_flag_; 00182 bool v_flag_; 00183 00184 // simulator support 00185 char* stack_; 00186 bool pc_modified_; 00187 int icount_; 00188 00189 // registered breakpoints 00190 Instr* break_pc_; 00191 instr_t break_instr_; 00192 }; 00193 00194 } } // namespace assembler::arm 00195 00196 #endif // defined(__arm__) 00197 00198 #endif // V8_SIMULATOR_ARM_H_